This invention relates to a phase locked loop (PLL) circuit for use in a semiconductor integrated circuit to generate a clock signal, particularly to a PLL circuit including a voltage controlled oscillator capable of changing an oscillating frequency characteristic against a control voltage and to a control method thereof.
A conventional PLL circuit comprises a phase comparator, a charge pump, a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, which are connected one another in this order to form a feedback loop. The VCO has a fixed oscillating frequency characteristic representing oscillating frequency against control voltage. The oscillating frequency characteristic corresponds to a gain factor which may either change according to the control voltage or be fixed regardless of the control voltage. When the gain factor is fixed, the oscillating frequency is represented as a liner function of the control voltage.
The PLL circuit produces an output clock signal according to a reference clock signal so that a frequency of a divided clock signal from the frequency divider is equal to that of the reference clock signal.
In the PLL circuit, there is fear that the frequency of the output clock signal overshoots a target frequency by the time when the PLL circuit is locked at the target frequency.
Furthermore, when the frequency of the output clock signal goes over a frequency band of a feedback path of the PLL circuit, the clock signal disappears from the feedback path. Thus, there is a case where the PLL circuit can not be locked.
Such a conventional phase locked loop circuit is disclosed in Japanese Patent Unexamined Publication No. 6-342566.
The phase locked loop circuit disclosed in Japanese Patent Unexamined Publication No. 6-342566 includes a voltage controlled oscillator having two gain factors. However, the larger one of the gain factors is employed at the beginning of the operation to be locked quickly. Then the smaller one of the gain factors is employed after the phase locked loop circuit is locked once.